-------------------------------------------------------------------------------
-- axi_datamover_dre_mux4_1_x_n.vhd
-------------------------------------------------------------------------------
--
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--
-------------------------------------------------------------------------------
-- Filename:        axi_datamover_dre_mux4_1_x_n.vhd
--
-- Description:     
--                  
--  This VHDL file provides a 4 to 1 by N bits wide mux for the AXI Data Realignment 
--  Engine (DRE).                  
--                  
--                  
--                  
-- VHDL-Standard:   VHDL'93
-------------------------------------------------------------------------------
-- Structure:   
--              axi_datamover_dre_mux4_1_x_n.vhd
--
-------------------------------------------------------------------------------
-- Revision History:
--
--
-- Author:          DET
--
-- History:
--   DET   04/19/2011       Initial Version for EDK 13.3
--  
--
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use ieee.STD_LOGIC_UNSIGNED.all;
use ieee.std_logic_arith.all;

         
         
-------------------------------------------------------------------------------
-- Start 4 to 1 xN Mux
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------  
Entity axi_datamover_dre_mux4_1_x_n is
   generic (
      
      C_WIDTH : Integer := 8
        -- Sets the bit width of the 4x Mux slice
      
      ); 
   port ( 
       Sel    : In  std_logic_vector(1 downto 0);
         -- Mux select control
       
       I0     : In  std_logic_vector(C_WIDTH-1 downto 0);
         -- Select 0 input
       
       I1     : In  std_logic_vector(C_WIDTH-1 downto 0);
         -- Select 1 input
       
       I2     : In  std_logic_vector(C_WIDTH-1 downto 0);
         -- Select 2 input
       
       I3     : In  std_logic_vector(C_WIDTH-1 downto 0);
         -- Select 3 input
       
       Y      : Out std_logic_vector(C_WIDTH-1 downto 0)
         -- Mux output value
       
      );
end entity axi_datamover_dre_mux4_1_x_n; --  

Architecture implementation of axi_datamover_dre_mux4_1_x_n is

begin
    
   -------------------------------------------------------------
   -- Combinational Process
   --
   -- Label: SELECT4_1
   --
   -- Process Description:
   --   This process implements an 4 to 1 mux.
   --
   -------------------------------------------------------------
   SELECT4_1 : process (Sel, I0, I1, I2, I3)
      begin
   
         case Sel is

           when "00" =>
               Y <= I0;
               
           when "01" =>
               Y <= I1;
               
           when "10" =>
               Y <= I2;
               
           when "11" =>
               Y <= I3;
               
           when others =>
               Y <= I0;
               
         end case;
         
      end process SELECT4_1; 

end implementation; -- axi_datamover_dre_mux4_1_x_n
 
 
-------------------------------------------------------------------------------
-- End 4 to 1 xN Mux
-------------------------------------------------------------------------------
      



